There is currently an ongoing drive toward the downscaling of device dimensions in virtually all aspects of electronic device manufacturing. Smaller electronic devices tend to be more popular than larger, more bulky devices when both devices have substantially equivalent capabilities. Accordingly, being able to fabricate smaller components would clearly tend to facilitate the production of smaller devices that incorporate those components. However, driving down component size often also means driving down the space between components, which may cause isolation issues.
In memory devices that include an array of tightly-packed memory cells, second bit effect and program disturb are phenomena that may impact the values stored in the memory cells. Improved isolation mechanisms can reduce the impact of these phenomena. However, with ever decreasing component sizes, isolation mechanisms must also continue to evolve.
Due to the high level of integration of devices and the large number of circuits on a single chip, interconnections are often no longer made by means of a single level of interconnections. Instead, at least two and sometimes more conductor interconnection levels may be formed, with each interconnection level having a pattern of wiring trenches being separated from the others by an insulating layer. Trenches may also be used for isolation. However, as even some of the trenches become smaller in size, filling the small spaces may become difficult. It may also be difficult to integrate vertical channel arrays with planar channel periphery circuits.
Accordingly, it may be desirable to provide an improved mechanism for filling small spaces in a semiconductor device such as a memory array. It may also be desirable to develop a mechanism for integrating vertical channel arrays with planar channel periphery circuits.